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fn8666 rev 4.00 page 1 of 24 apr 19, 2018 fn8666 rev 4.00 apr 19, 2018 isl8117 synchronous step-down pwm controller datasheet the isl8117 is a synchronous buck controller used to generate pol voltage rails and bias voltag e rails for a wide variety of applications in industrial an d general purpose segments. its wide input and output voltage ranges make it suitable for telecommunication and after-mark et automotive applications. the isl8117 uses the valley current modulation technique to bring hassle-free power supply design with a minimal number of components and complete protection from unwanted events. the isl8117 offers programmable soft-start and enable functions along with a power-good indicator for ease of supply rail sequencing and other housek eeping requirements. in ideal situations, a complete power supply circuit can be designed with 10 external components and provide ov/oc/ot protections in a space conscious 16 ld 4mmx4mm qfn or easy to assemble 6.4mmx5mm 16 ld htssop package. both packages use an epad to improve thermal dissipation and noise immunity. low pin count, fewer external components, and default internal values makes the isl8117 an ideal solution for quick to market si mple power supply designs. the isl8117 uses internal loop compensation and single resistor settings for other functions such as operating frequency and overcurrent protection. its current mode control with v in feed- forward enables it to cover variou s applications even with fixed internal compensations. the unique dem/skipping mode at light-load dramatically lowe rs standby power consumption with consistent output ripple over different load levels. related literature for a full list of related documents, visit our website ? isl8117 product page features ? wide input voltage range: 4.5v to 60v ? wide output voltage range: 0.6v to 54v ? light-load efficiency enhancement - low ripple diode emulation mode with pulse skipping ?programmable soft-start ? supports prebiased output with sr soft-start ? programmable frequency: 100khz to 2mhz ?external sync ?pgood indicator ?forced pwm ? adaptive shoot-through protection ? no external current sense resistor - use lower mosfet r ds(on) ? complete protection - overcurrent, overvoltage, ov er-temperature, undervoltage ? pb-free (rohs compliant) applications ? plc and factory automation ?amusement machines ?security surveillance ? servers and data centers ?switchers and routers ? telecom and datacom ?led panels figure 1. typical application figure 2. efficiency vin vout isen pgood clkout ss/trk rt en phase lgate ocs vcc5v ugate boot vin extbias 16 1 2 3 4 5 6 7 10 11 12 13 14 15 mod sync sgnd fb 8 pgnd 9 84 86 88 90 92 94 96 98 100 0246810121416 output current (a) efficiency (%) v in = 24v v in = 36v v in = 18v v in = 48v v in = 60v
isl8117 fn8666 rev 4.00 page 2 of 24 apr 19, 2018 table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical application schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 internal 5v linear regulator (vcc5v) and ex ternal vcc bias supply (ext bias) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 enable and soft-start operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 output voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 tracking operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 light-load efficiency enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 prebiased power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 frequency synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 gate control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 adaptive dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 internal bootstrap diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-good indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 protection circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 over-temperature protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 feedback loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 general powerpad design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 component selection guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 mosfet considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output inductor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 l16.4x4a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 m16.173a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
isl8117 fn8666 rev 4.00 page 3 of 24 apr 19, 2018 pin configurations isl8117 16 ld 4x4 qfn top view isl8117 16 ld htssop top view ordering information part number ( notes 2 , 3 ) part marking temp. range (c) tape and reel (units) ( note 1 ) package (rohs compliant) pkg. dwg. # isl8117frz 81 17frz -40 to +125 - 16 ld 4x4 qfn l16.4x4a isl8117frz-t 81 17frz -40 to +125 6k 16 ld 4x4 qfn l16.4x4a isl8117frz-t7a 81 17frz -40 to +125 250 16 ld 4x4 qfn l16.4x4a isl8117fvez 8117 fvez -40 to +125 - 16 ld htssop m16.173a isl8117fvez-t 8117 fvez -40 to +125 2.5k 16 ld htssop m16.173a isl8117fvez-t7a 8117 fvez -40 to +125 250 16 ld htssop m16.173a ISL8117EVAL1Z evaluation board for htssop isl8117demo1z demonstration board for htssop isl8117eval2z evaluation board for qfn isl8117demo2z demonstration board for qfn isl8117demo3z demonstration board for qfn isl8117demo4z demonstration board for qfn notes: 1. refer to tb347 for details about reel specifications. 2. these pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). pb -free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), refer to the isl8117 product information page. for more information about msl, refer to tb363 . 1 3 4 15 clkout mod/sync pgood rt en extbias vin boot 16 14 13 2 12 10 9 11 6 578 ugate phase isen vcc5v ss/trk fb pgnd lgate/ocs sgnd 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 extbias en clkout mod/sync pgood rt fb ss/trk vin ugate phase isen vcc5v lgate/ocs pgnd boot sgnd pin descriptions pin # (htssop) pin # (qfn) pin name function 3 1 clkout clock signal output. the frequency of the clock signal is the switching frequency set by the resistor from rt to ground . 4 2 mod/sync dual function pin. connect this pin to vcc5v to select diode emulation mode with pulse skipping at light-load. while connected to ground or floating, the contro ller operates in pwm mode at light-load. connect this pin to an external clock for synchronization. the controller operates in pwm mode at light-load when synchronized with an external clock. 5 3 pgood open-drain logic output used to indicate the status of output voltage. this pin is pulled down when the output is not wi thin 11% of the nominal voltage or the en pin is pulled low.
isl8117 fn8666 rev 4.00 page 4 of 24 apr 19, 2018 6 4 rt a resistor from this pin to ground adjusts the switching frequency from 100khz to 2mhz. the switching frequency of the pwm controller is determined by the resistor, r t as shown in equation 1 . where f sw is the switching frequency in mhz. when this pin is tied to ground, the output frequency is set to 300khz. when this pin is tied to vcc5v or floati ng, the output frequency is set to 600khz. 7 5 ss/trk dual function pin. when used for soft-starting control, a soft-start capacitor is connecte d from this pin to ground. a regulated 2 a soft-starting current charges up the soft-start capacito r. value of the soft-start capacitor sets the output voltage ramp. when used for tracking control, an external supply rail is co nfigured as the master and the output voltage of the master supply is applied to this pin using a resistor divider. the output voltage will track the master supply voltage. 8 6 fb output feedback input. connect fb to a resistive voltage divider from the output to sgnd to adjust the output voltage. 9 7 pgnd power ground connection. this pin should be connected to the sources of the lower mosfet s and the (-) terminals of the external input capacitors. 10 8 lgate/ocs low-side mosfet gate driver output and oc set pin. connect a 1k to 30k resistor between this pin and ground to set the overcurrent threshold. if there is no re sistor connected from this pin to gnd, the overcurrent threshold is automatically set to the same point as a 10k resistor. 11 9 vcc5v output of the internal 5v linear regulator. this output supplies bias for the ic, the low-side gate driver and the inte rnal boot circuitry for the high-side gate driver. the vcc5v pin mu st always be decoupled to power ground with a minimum of 4.7f ceramic capacitor placed very close to the pin. do no t allow the voltage at vcc5v to exceed vin at any time. to prevent excessive current through the vcc5v pin to the vin pin, a resistor can be connected from the vin pin to the power supply. 12 10 isen current sense signal input. this pi n is used to monitor the voltage drop acro ss the lower mosfet for current loop feedb ack and overcurrent protection. 13 11 phase phase node connection. this pin is connected to the junc tion of the upper mosfet?s source, output filter inductor, and lower mosfet?s drain. 14 12 ugate high-side mosfet gate driver output. 15 13 boot bootstrap pin to provide bias for high-side driver. the po sitive terminal of the bootstra p capacitor connects to this p in. the bootstrap diode is integrated to help reduce total cost and reduce layout complexity. 16 14 vin this pin should be tied to the input rail. it provides po wer to the internal linear drive circuitry and is also used by the feed-forward controller to adjust the amplitude of the pwm sawtooth. decouple this pin with a small ceramic capacitor (0.1f to 1f) to ground. 1 15 extbias input from an optional external 5v bias supply. there is an internal switch from this pin to vcc5v. this switch close s and supplies the ic power, bypassing the internal linear regulator, when voltage at extbias is higher than 4.7v (typ). do not allow voltage at the extbias pin to exceed vin at any time. to prevent excessive current th rough the extbias pin to the vin pin, a resistor can be connected from the vin pin to the power supply. decouple this pin to ground with a smal l ceramic capacitor (0.1f to 1f) when it is in use, otherwise tie this pin to ground. do not float this pin. 2 16 en this pin provides an enable/disable fu nction. the output is disabled when the pi n is pulled to ground. when the voltage on the pin reaches 1.6v, the output becomes active. when the pi n is floating, it will be enabled in default by internal pull-up . --sgnd epad this is the small-signal ground common to all control circuitr y. it is suggested to route this separately from the high current ground (pgnd). sgnd and pgnd can be tied together if there is one solid ground plane with no noisy currents around the chip. all voltage levels ar e measured with respect to this pin. epad at ground potential. epad is connected to sgnd internally. however, it is highly recommended to solder it directly to ground plane for better thermal performance and noise immunity. pin descriptions (continued) pin # (htssop) pin # (qfn) pin name function r t 39.2 f sw ----------- 1.96 C ?? ?? k ? ? = (eq. 1)
isl8117 fn8666 rev 4.00 page 5 of 24 apr 19, 2018 block diagram 5vcc 5vcc boot ugate phase lgate/ocs pgnd pgnd adaptive dead time v/i sample timing por enable bias supplies reference fault latch ov/uv oc fb sw thres. pgood en vin vcc5v extbias mod/sync fb ss/trk isen 2a ss/trk ss/trk + _ + _ 0.6v ref + _ 1.75v reference duty cycle ramp generator clock rt sgnd lgate/ocs lgate/ocs oc clkout pwm current sample current sample same state for 2 clock cycles required to latch overcurrent fault vin 5vcc see note 6 figure 3. block diagram
isl8117 fn8666 rev 4.00 page 6 of 24 apr 19, 2018 typical application schematics figure 4. ISL8117EVAL1Z evaluation board schematic figure 5. isl8117eval2z evaluation board schematic q1a buk9k17-60ex c3 0.047u/25v r9 2 3.3v/6a vout 1 r6 76.8k c20 470p/100v r2 11k gnd 1 r5 10k c9 200u/6.3v u1 isl8117 extbias 1 en 2 clkout 3 mod/sync 4 pgood 5 rt 6 ss/trk 7 fb 8 pgnd 9 lgate/ocs 10 vcc5 11 isen 12 phase 13 ugate 14 boot 15 vin 16 sgnd 17 l1 3.3u 4.5 - 60v vin 1 c1 4.7u/10v r11 5.1 c5 0.1u/25v q1b r10 2.2 r7 3k r4 22k c4 0.1u/100v c6 220p/50v c8 100u/100v r3 10k r1 49.9k gnd 1 c2 0.22u/25v 18v~60v 12v/20a r6 0 c8 220u/100v r12 1 q2 bsc067n06ls3 u2 isl80138 in 2 en 7 gnd 8 adj 12 out 14 vout 1 c5 0.01u/25v r1 49.9k c1 4.7u/10v r9 10 c7 100p/100v r4 91k gnd 1 r7 5.1k q3 bsc067n06ls3 r5 10k vin 1 r10 10k c6 220p/50v c9 330u/35v c4 0.1u/100v r11 30.9k l1 3.3uh q1 bsc067n06ls3 c3 0.047u/25v u1 isl8117 clkout 1 mod/sync 2 pgood 3 rt 4 ss/trk 5 fb 6 pgnd 7 lgate/ocs 8 vcc5v 9 isen 10 phase 11 ugate 12 boot 13 vin 14 exbias 15 en 16 sgnd 17 r2 2.62k r8 22 gnd 1 d1 dnp q4 bsc067n06ls3 c2 1u/25v c16 4.7u/10v r3 5.1k
isl8117 fn8666 rev 4.00 page 7 of 24 apr 19, 2018 absolute maximum rating s thermal information vcc5v to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v extbias to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v vin to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +62.5v boot/ugate to phase . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc5v+0.3v phase and isen to gnd . . . . . . . . . . . . . -5v (<20ns)/-0.3v (dc) to +62.5v en, pgood, ss/trk, fb to gnd. . . . . . . . . . . . . . . . . -0.3v to vcc5v+0.3v lgate/ocs to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc5v+0.3v rt, mod/sync, clkout to gnd. . . . . . . . . . . . . . . . . -0.3v to vcc5v+0.3v vcc5v short-circuit to gnd duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1s esd rating human body model (tested per js-001-2010) . . . . . . . . . . . . . . . . . . 4kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 400v charge device model (tested per jesd22-c101e). . . . . . . . . . . . . . . 2kv latch-up (tested per jesd78d; class ii, level a, +125c) . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 16 ld qfn package ( notes 4 , 5 ) . . . . . . . . 40 2.5 16 ld htssop package ( notes 4 , 5 ) . . . . . 35 4.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . .-55c to +150c maximum operating temperature . . . . . . . . . . . . . . . . . . .-40c to +125c maximum storage temperature. . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c vin to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 60v vcc5v to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1v to 5.5v extbias to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1v to +5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the component mounted on a high-e ffective thermal conductivity test board with ?direct attach? fe atures. see tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions un less otherwise noted. refer to ? block diagram ? on page 5 and ? typical application schematics ? on page 6 . v in = 4.5v to 60v, or vcc5v = 5v 10%, c_vcc5v = 4.7f, t a = -40c to +125c, typical values are at t a = +25c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +125c. parameter symbol test conditions min ( note 9 )typ max ( note 9 )unit v in supply input voltage range v in 4.5 60.0 v v in supply current shutdown current ( note 6 )i vinq en = 0 pgood is floating 5 10 a operating current ( note 8 )i vinop pgood is floating 2.5 4 ma vcc5v supply ( note 6 ) operation voltage v cc v in = 12v, i l = 0ma 4.85 5.1 5.4 v internal ldo output voltage v in = 4.5v, i l = 30ma 4.1 4.4 v internal ldo output voltage v in > 5.6v, i l = 75ma 4.75 5.05 v maximum supply current of internal ldo i vcc_max v vcc5v = 0v, v in = 12v 120 ma extbias supply ( note 6 ) switch over threshold voltage, rising v ext_thr extbias voltage 4.5 4.7 4.9 v switch over threshold voltage, falling v ext_thf extbias voltage 4.2 4.5 4.65 v internal switch on-resistance r ext v in = 12v 1.5 undervoltage lockout undervoltage lockout, rising v uvlothr v in voltage, 0ma on vcc5v 3.7 3.90 4.2 v undervoltage lockout, falling v uvlothf v in voltage, 0ma on vcc5v 3.35 3.50 3.85 v en threshold en rise threshold v enss_thr v in > 5.6v 1.25 1.60 1.95 v en fall threshold v enss_thf v in > 5.6v 1.05 1.25 1.55 v en hysteresis v enss_hyst v in > 5.6v 180 350 500 mv soft-start current ss/trk soft-start charge current i ss ss/trk = 0v 2.00 a
isl8117 fn8666 rev 4.00 page 8 of 24 apr 19, 2018 default internal minimum soft-starting default internal output ramping time t ss_min ss/trk open 1.5 ms power-good monitors pgood upper threshold v pgov 109 112.5 115 % pgood lower threshold v pguv 85 87.5 92 % pgood low level voltage v pglow i_sink = 2ma 0.35 v pgood leakage current i pglkg pgood = 5v 20 150 na pgood timing v out rising threshold to pgood rising ( note 11 )t pgr 1.1 5 ms v out falling threshold to pgood falling t pgf 75 s reference section internal reference voltage v ref 0.600 v reference voltage accuracy t a = 0c to +85c -0.75 +0.75 % t a = -40c to +125c -1.00 +1.00 % fb bias current i fblkg -40 0 40 na pwm controller error amplifiers dc gain 88 db gain-bw product gbw 8 mhz slew rate sr 2.0 v/s pwm regulator minimum off time t off_min 308 ns minimum on time t on_min 40 ns peak-to-peak sawtooth amplitude d v ramp v in = 20v 1.0 v v in = 12.0v 0.6 v ramp offset 1.0 v switching frequency switching frequency f sw r t = 36k 890 1050 1195 khz switching frequency r t = 16.5k 1650 2000 2375 khz switching frequency rt pin connect to gnd 250 300 350 khz switching frequency rt pin connect to vcc5v or float 515 600 645 khz rt voltage v rt r t = 36k 770 mv clock output and synchronization clkout output high vclkh i source = 1ma vcc5v - 0.3 v clkout output low v clkl i sink = 1ma 0.3 v clkout frequency f clk r t = vcc5v 515 600 645 khz sync synchronization range f sync r t = 36k 1230 2200 khz diode emulation mode detection mod/sync threshold high v modethh 1.1 1.6 2.1 v mod/sync hysteresis v modehyst 200 mv diode emulation phase threshold ( note 10 )v cross v in = 12v -3 mv electrical specifications recommended operating conditions un less otherwise noted. refer to ? block diagram ? on page 5 and ? typical application schematics ? on page 6 . v in = 4.5v to 60v, or vcc5v = 5v 10%, c_vcc5v = 4.7f, t a = -40c to +125c, typical values are at t a = +25c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 9 )typ max ( note 9 )unit
isl8117 fn8666 rev 4.00 page 9 of 24 apr 19, 2018 pwm gate driver source current i gsrc 2000 ma sink current i gsnk 2000 ma upper drive pull-up r ug_up vcc5v = 5.0v 1.5 upper drive pull-down r ug_dn vcc5v = 5.0v 1.5 lower drive pull-up r lg_up vcc5v = 5.0v 1.0 lower drive pull-down r lg_dn vcc5v = 5.0v 0.8 upper drive rise time t gr_up c out = 1000pf 9.0 ns upper drive fall time t gf_up c out = 1000pf 8.0 ns lower drive rise time t gr_dn c out = 1000pf 7.0 ns lower drive fall time t gf_dn c out = 1000pf 6.1 ns overvoltage protection ovp threshold v ovth 116 121 127 % overcurrent protection oc set current source i ocset-cs lgate/ocs = 0v 9 10.5 11.5 a over-temperature over-temperature shutdown t ot-th 160 c over-temperature hysteresis t ot-hys 15 c notes: 6. in normal operation, where the device is supplied with voltage on the vin pin, the vcc5v pin provides a 5v output capable of 75ma (min). when the device is supplied by an external 5v supply on the extbias pin, the internal ldo regulator is disabled. the voltage at vcc5v sh ould not exceed the voltage at vin at any time. (refer to ? pin descriptions ? on page 3 for more details.) 7. this is the total sh utdown current with v in = 5.6v and 60v. 8. operating current is the supply current consumed when the device is active but not switching. it does not include gate drive current. 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 10. threshold voltage at phase pin for turning off the bottom mosfet during dem. 11. when soft-start time is less than 4.5ms, t pgr increases. with internal soft-start (the fastest soft-start time), t pgr increases close to its max limit 5ms. electrical specifications recommended operating conditions un less otherwise noted. refer to ? block diagram ? on page 5 and ? typical application schematics ? on page 6 . v in = 4.5v to 60v, or vcc5v = 5v 10%, c_vcc5v = 4.7f, t a = -40c to +125c, typical values are at t a = +25c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 9 )typ max ( note 9 )unit
isl8117 fn8666 rev 4.00 page 10 of 24 apr 19, 2018 typical performance curves oscilloscope plots are taken using the isl8117eval2z evaluation board, v in = 18 to 60v, v out = 12v, i out = 20a unless otherwise noted. figure 6. shutdown current vs temperature figure 7. quiescent cu rrent vs temperature figure 8. vcc5v load regulation figure 9. vcc5v line regulation figure 10. switching freq uency vs temperature (r t = 36k ? ) figure 11. switching frequency vs v in temperature (c) i v i n q ( a ) 0 1 2 3 4 5 6 7 8 9 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 i v i n o p ( m a ) temperature (c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 1 2 3 4 5 6 0 20 40 60 80 100 120 load current (ma) vcc5v (v) 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 0 102030405060 v in (v) vcc5v (v) f sw (khz) temperature (c) 1000 1010 1020 1030 1040 1050 1060 1070 1080 1090 1100 -40 -25 -10 5 20 35 50 65 80 95 110 125 v in (v) f sw (khz) 0 50 100 150 200 250 300 350 0 5 10 15 20 25 30 35 40 45 50 55 60
isl8117 fn8666 rev 4.00 page 11 of 24 apr 19, 2018 figure 12. reference voltage vs temperature figure 13. normalized output voltage vs voltage on soft-start pin figure 14. ccm mode efficiency figure 15. dem mode efficiency figure 16. ccm mode load regulation figure 17. ccm mode line regulation typical performance curves oscilloscope plots are taken using the isl8117eval2z evaluation board, v in = 18 to 60v, v out = 12v, i out = 20a unless otherwise noted. (continued) v r e f ( m v ) temperature (c) 595 596 597 598 599 600 601 602 603 604 605 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 soft-start pin voltage (v) normalized output voltage (%) 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 v in = 18v v in = 24v v in = 36v v in = 48v v in = 60v i out (a) efficiency (%) 20 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 i out (a) efficiency (%) v in = 18v v in = 24v v in = 36v v in = 48v v in = 60v 20 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 101214161820 output current (a) regulation (%) v in = 36v v in = 48v v in = 60v v in = 18v v in = 24v -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 18 24 30 36 42 48 54 60 i o = 20a v in (v) regulation (%) i o = 10a i o = 0a
isl8117 fn8666 rev 4.00 page 12 of 24 apr 19, 2018 figure 18. input current comparison with mode = ccm/dem, v in = 48v figure 19. phase, lgate, cl kout and inductor current waveforms figure 20. output ripple, mode = ccm f igure 21. output ripple, mode = dem figure 22. start-up waveforms; mode = ccm, load = 0a, v in =48v figure 23. start-up waveforms; mode = dem, load = 0a, v in = 48v typical performance curves oscilloscope plots are taken using the isl8117eval2z evaluation board, v in = 18 to 60v, v out = 12v, i out = 20a unless otherwise noted. (continued) 0.001 0.01 0.1 1 10 0.01 0.1 1 10 i in (dem) i in (ccm) i in (a) i out (a) i l 5a/div lgate 5v/div clkout 5v/div phase 50v/div 1s/div 4s/div v out 50mv/div v out 50mv/div no load, v in = 48v 20a load, v in = 48v 4s/div v out 50mv/div v out 50mv/div no load, v in = 48v 20a load, v in = 48v 1ms/div 4ms/div v out 5v/div lgate 5v/div clkout 5v/div i l 10a/div dem to ccm transition extbias kick-in boot cap refresh 4ms/div v out 5v/div lgate 5v/div clkout 5v/div i l 5a/div extbias kick-in boot cap refresh burst mode operation
isl8117 fn8666 rev 4.00 page 13 of 24 apr 19, 2018 figure 24. start-up waveforms; mode = ccm, load = 0a , v in = 48v figure 25. start-up waveforms; mode = dem, load = 0a, v in = 48v figure 26. tracking; v in = 48v, load = 0a , mode = ccm figure 27. frequency synchronization; v in = 48v, load = 0a , default f sw = 300khz, sync f sw = 400khz figure 28. load transient response; v in = 48v, 0a to 20a 1a/s step load, ccm mode figure 29. ocp response, output short-circuited from no load to ground and released, ccm mode, v in = 48v typical performance curves oscilloscope plots are taken using the isl8117eval2z evaluation board, v in = 18 to 60v, v out = 12v, i out = 20a unless otherwise noted. (continued) 20ms/div v out 5v/div ss 1v/div en 5v/div pgood 5v/div 20ms/div v out 5v/div ss 1v/div en 5v/div pgood 5v/div 1ms/div ss 500mv/div v out 10v/div pgood 5v/div 800ns/div i l 5a/div lgate 5v/div sync 5v/div clkout 5v/div 400s/div v out 500mv/div i out 10a/div 40ms/div v out 10v/div i l 20a/div ss 2v/div pgood 5v/div
isl8117 fn8666 rev 4.00 page 14 of 24 apr 19, 2018 functional description general description the isl8117 integrates control circuits for a synchronous buck converter. the driver and protection circuits are also integrated to simplify the end design. the part has an independent enable/disable control line en, which provides a flexible power-up sequencing and a simple vin uvp implementation. the soft-sta rt time is programmable by adjusting the soft-start capacitor connected from ss/trk. the valley current mode control scheme with input voltage feed-forward ramp simplifies loop compensation and provides excellent rejection to input voltage variation. input voltage range the isl8117 is designed to operate from input supplies ranging from 4.5v to 60v. the input voltage range can be effectively limited by the available minimum pwm off-time as shown in equation 2 . where, v d1 = sum of the parasitic voltage drops in the inductor discharge path, including the lower fet, inductor and pc board. v d2 = sum of the voltage drops in the charging path, including the upper fet, inductor and pc board resistances. t off(min) = 308ns. the maximum input voltage and minimum output voltage is limited by the minimum on-time (t on(min) ) as shown in equation 3 . where, t on(min) = 40ns in ccm and 60ns in dem. internal 5v linear regulator (vcc5v) and external vcc bias supply (extbias) all the isl8117 functions can be internally powered from an on-chip, low dropout 5v regulator or an external 5v bias voltage through the extbias pin. bypass the linear regulator?s output (vcc5v) with a 4.7f capacitor to the power ground. the isl8117 also employs an undervoltage lock out circuit, which disables all regulators when vcc5v falls below 3.5v. the internal ldo can source over 75ma to supply the ic, power the low-side gate driver, and charge the boot capacitor. when driving large fets at high switching frequency, little or no regulator current may be available for external loads. for example, a single large fet with 15nc total gate charge requires 15nc x 300khz = 4.5ma (15nc x 600khz = 9ma). also, at higher input voltages with larger fets, the power dissipation across the internal 5v will incr ease. excessive dissipation across this regulator must be avoided to prevent junction temperature rise. thermal protection may be triggered if die temperature increases above +160c due to excessive power dissipation. when large mosfets are used, an external 5v bias voltage can be applied to the extbias pin to alleviate excessive power dissipation. voltage at the extb ias pin must always be lower than the voltage at the vin pin to prevent biasing of the power stage through extbias and vcc5v. an external uvlo circuit might be necessary to ensure smooth soft-starting. the internal ldo has an overcurrent limit of typically 120ma. for better efficiency, connect vcc5v to vin for 5v 10% input applications. enable and soft-start operation pulling the en pin high or low can enable or disable the controller. when the en pin voltage is higher than 1.6v, the controller is enabled to initialize its internal circuit. after the vcc5v pin reaches the uvlo threshold, isl8117 soft-start circuitry becomes active. the internal 2a charge current begins charging up the soft-start capacitor connected from the ss/trk pin to gnd. the voltage error amplifier reference voltage is clamped to the voltage on the ss/trk pin. the output voltage thus rises from 0v to regulation as ss/trk rises from 0v to 0.6v. charging of the soft-start capacitor continues until the voltage on the ss/trk pin reaches 3v. typical applications for isl8 117 use programmable analog soft-start or ss/trk pin for tracking. the soft-start time can be set by the value of the soft-start capacitor connected from the ss/trk to gnd. inrush current during start-up can be alleviated by adjusting the soft-starting time. the typical soft-start time is set according to equation 4 : when the soft-starting time set by external c ss or tracking is less than 1.5ms, an internal soft-start circuit of 1.5ms takes over the soft-start. pgood will toggle to high when the corresponding output is up and in regulation. pulling the en low disables the pwm output and internal ldo to achieve low standby current. the ss/trk pin will also be discharged to gnd by an internal mosfet with 70 r ds(on) . output voltage programming the isl8117 provides a precision 0.6v internal reference voltage to set the output voltage. based on this internal reference, the output voltage can be set from 0.6v up to a level determined by the input voltage, the maximum duty cycle, and the conversion efficiency of the circuit. a resistive divider from the outp ut to ground sets the output voltage. the center point of the divider shall be connected to the fb pin. the output voltage value is determined by equation 5 . where r 1 is the top resistor of the feedback divider network and r 2 is the bottom resistor connected from fb to ground. v in min ?? v out v d1 + 1t C off min ?? frequency ? --------------------------------------------------------------- ----------- ?? ?? ?? v d2 v d1 C + ? (eq. 2) v in max ?? v out t on min ?? frequency ? ------------------------------------------------------------- - ?? ?? ?? ? (eq. 3) t ss 0.6v c ss 2 ? a ----------- ?? ?? = (eq. 4) v out 0.6v r 1 r 2 + r 2 -------------------- - ?? ?? ?? = (eq. 5)
isl8117 fn8666 rev 4.00 page 15 of 24 apr 19, 2018 tracking operation the isl8117 can be set up to track an external supply. to implement tracking, a resistive divider is connected between the external supply output and ground. the center point of the divider shall be connected to the ss/trk pin of the isl8117. the resistive divider ratio sets the ramping ratio between the two voltage rails. to implement coinci dent tracking, set the tracking resistive divider ratio exactly th e same as the isl8117 output resistive divider given by equation 5 . make sure that the voltage at ss/trk is greater than 0.6v when the master rail reaches regulation. to minimize the impact of the 2a soft-start current on the tracking function, it is recommen ded to use resistors of less than 10k for the tracking resistive divider. when overcurrent protection (ocp) is triggered, the internal minimum soft-start circuit determ ines the ocp soft-start hiccup. light-load efficiency enhancement when mod/sync is tied to vcc5v, the isl8117 operates in high efficiency diode emulation mode and pulse skipping mode in light-load condition. the inductor current is not allowed to reverse (discontinuous operation). at very light-loads, the converter goes into diode emulation and triggers the pulse skipping function. in pulse skipping mode, the upper mosfet remains off until the output voltage drops to the point the error amplifier output goes above the pulse skipping mode threshold. the minimum t on in the pulse skipping mode is 60ns. prebiased power-up the isl8117 has the ability to soft-start with a prebiased output. the output voltage would not be pulled down during prebiased start-up. the pwm is not active until the soft-start ramp reaches the output voltage times the resistive divider ratio. overvoltage protection is alive during soft-start. frequency selection switching frequency selection is a trade-off between efficiency and component size. low switching frequency improves efficiency by reducing mosfet switching loss. to meet the output ripple and load transient requ irements, operat ion at a low switching frequency would require larger inductance and output capacitance. the switching frequency of the isl8117 is set by a resistor connected from the rt pin to gnd according to equation 1 . the frequency setting curve shown in figure 30 assists in selecting the correct value for r t . frequency synchronization the mod/sync pin may be used to synchronize isl8117 to an external clock or the clkout pin of another isl8117. when the mod/sync pin is connected to the clkout pin of another isl8117, the two controllers operate in synchronization. when the mod/sync pin is connected to an external clock, the isl8117 will synchronize to this external clock frequency. for proper operation, the frequency set by resistor r t should be lower than the external clock frequency. when frequency synchronization is in action, the controllers will enter forced continuous current mode at light-load. clkout pin outputs a clock signal with a 280ns pulse width. the signal frequency is the same as the frequency set by the resistor from rt pin to ground. the signal rising edge is in line with the pwm falling edge. gate control logic the gate control logic translates the pwm signal into gate drive signals providing amplification, level shifting, and shoot-through protection. the gate driver has circuitry that helps optimize the ic performance over a wide rang e of operational conditions. mosfet switching times can vary dr amatically from type to type and with input voltage, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower mosfets. shoot-thr ough control logic provides a 16ns dead time to ensure that both the upper and lower mosfets will not turn on simultan eously causing a shoot-through condition. figure 30. r t vs switching frequency f sw 0 500 1000 1500 2000 2500 3000 3500 0 20 40 60 80 100 120 140 160 180 200 r t (k) f sw (khz)
isl8117 fn8666 rev 4.00 page 16 of 24 apr 19, 2018 gate driver the low-side gate driver is supplied from vcc5v and provides a 2a peak sink and source current. the high-side gate driver is also capable of delivering the same currents as the low-side gate driver. gate-drive voltage for the upper n-channel mosfet is generated by a flying capacitor boot circuit. a boot capacitor connected from the boot pin to the phase node provides power to the high-side mosfet driver. to limit the peak current in the ic, an external resistor can be placed between the boot pin and the boot capacitor. this small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and th e fet?s input capacitance. at start-up, the low-side mosfet turns on first and forces phase to ground in order to charge the boot capacitor to 5v. after the low-side mosfet turns off, the hi gh-side mosfet is turned on by closing an internal switch between boot and ugate. this provides the necessary gate-to-source voltage to turn on the upper mosfet, an action that boosts the 5v gate drive signal above v in . the current required to drive the upper mosfet is drawn from the internal 5v regulator. for optimal emi performance or re ducing phase node ringing, a small resistor might be placed between the boot pin to the positive terminal of the bootstrap capacitor. adaptive dead time the isl8117 incorporates an adap tive dead time algorithm on the synchronous buck pwm contro ller that optimizes operation with varying mosfet conditio ns. this algorithm provides approximately 16ns de ad time between the switching of the upper and lower mosfets. this dead time is adaptive and allows operation with different mosfets without having to externally adjust the dead time using a resist or or capacitor. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a threshold of 1v, at whic h time the ugate is released to rise. adaptive dead time circuitry monitors the upper mosfet gate voltage during ugate turn-off. once the upper mosfet gate-to-source voltage has dropped below a threshold of 1v, the lgate is allowed to rise. it is recommended to not use a resistor between ugate and lgate and the respective mosfet gates as it may interfere with the dead time circuitry. internal bootstrap diode the isl8117 has an integrated bootstrap diode to help reduce total cost and reduce layout complexity. simply adding an external capacitor across the bo ot and phase pins completes the bootstrap circuit. the bootstra p capacitor can be chosen from equation 6 . where q gate is the amount of gate charge required to fully charge the gate of the upper mosfet. the ? v boot term is defined as the allowable droop in the rail of the upper drive. as an example, suppose an upper mosfet has a gate charge (q gate ) of 25nc at 5v and also assume the droop in the drive voltage over a pwm cycle is 200mv. based on the calculation, a bootstrap capacitance of at least 0.125f is required. the next larger standard value capacitance of 0.22f should be used. a good quality ceramic capacitor is recommended. the internal bootstrap schottky diode has a resistance of 1.5 (typical) at 800ma. combined with the resistance r boot , this could lead to the boot capacitor charging insufficiently in cases where the bottom mosfet is turned on for a very short period of time. if such circumst ances are expected, an additional external schottky diode may be added from vcc5v to the positive of the boot capacitor. r boot may still be necessary to lower emi due to fast turn-on of the upper mosfet. power-good indicator the power-good pin can be used to monitor the status of the output voltage. pgood will be tr ue (open drain) 1.1ms after the fb pin is within 11% of the reference voltage. there is no extra delay when the pgood pin is pulled low. protection circuits the converter output is monitored and protected against overload, light-load, and undervoltage conditions. undervoltage lockout the isl8117 includes uvlo protection, which keeps the device in a reset condition until a proper op erating voltage is applied. it also shuts down the isl8117 if the operating voltage drops below a predefined value. the controller is disabled when uvlo is asserted. when uvlo is asserted, pgood is valid and will be deasserted. boot ugate phase vcc_5v vin isl8117 figure 31. upper gate driver circuit c b r boot optional external schottky boot q gate ? v boot ----------------------- - ? (eq. 6)
isl8117 fn8666 rev 4.00 page 17 of 24 apr 19, 2018 overcurrent protection the controller uses the lower mosfet's on-resistance, r ds(on) , to monitor the current in the converter. the sensed voltage drop is compared with a threshold set by a resistor, r ocset , connected from the lgate/ocs pin to ground during the initiation stage before soft-start. during the init iation stage, a 10.5a current source from lgate/ocs pin crea tes a voltage drop on rocset. the voltage drop is then read and stored as the ocp comparator reference. r ocset can be calculated by equation 7 . where i oc is the desired overcurrent protection threshold and r cs is the value of the current sense resistor connected to the isen pin. the unit for r ds(on) is m and for r cs it is k . if an overcurrent is detected, the upper mosfet remains off and the lower mosfet remains on until the next cycle. as a result, the converter will skip a pulse. when the overload condition is removed, the converter will resume normal operation. if an overcurrent is detected fo r two consecutive clock cycles, the ic enters in a hiccup mode by turning off the gate driver and entering soft-start. the ic will st ay off for 50ms before trying to restart. the ic will continue to cycle through soft-start until the overcurrent condition is removed. hiccup mode is active during soft-start, so care must be taken to ensure that the peak inductor current does not exceed the overcurrent threshold during soft-start. because of the nature of this current sensing technique, and to accommodate a wide range of r ds(on) variations, the value of the overcurrent threshold should repr esent an overload current about 150% to 180% of the maximum operating current. if more accurate current protection is desired, place a current sense resistor in series with the lower mosfet source. when ocp is triggered, the ss/trk pin is pulled to ground by an internal mosfet for hiccup restart. when configured to track another voltage rail, the ss/trk pin rises up much faster than the internal minimum soft-start ramp. the voltage reference will then be clamped to the internal minimum soft-start ramp. thus, smooth soft-start hiccup is achieved even with the tracking function. for applications with large in ductor ripple current, it is recommended to use a larger r cs to reduce the current ripple into the isen pin to less than 6a which is the ocp comparator hysteresis. otherwise, when the load current approaches to the ocp trip point, the ocp comparat or can trip and reset in one switching cycle. the overcurren t condition cannot last for two consecutive cycles to force the ic into hiccup mode. instead, the ic will run in a half frequency pwm mode leading to a larger output ripple. overvoltage protection the overvoltage set point is set at 121% of the nominal output voltage set by the feedback resistors. in the case of an overvoltage event, the ic will attempt to bring the output voltage back into regulation by keeping the upper mosfet turned off and the lower mosfet turned on. if the overvoltage condition has been corrected and the output vo ltage returns to 110% of the nominal output voltage, both upper and lower mosfets will be turned off until the output voltage drops to the nominal voltage to start work in normal pwm switching. for lower control loop bandwidth applications, such as very low output voltage or very low switching frequency designs, the full load to no load transient respon se may be slow to cause an ovp false trigger. when ovp is triggered, the long lgate on-time will create a high negative inductor current leading to a higher than normal sink in current to the isen pin. it is recommended to limit the isen pin sink in current to less than 16a. otherwise, a false ocp hiccup operation may be triggered to cause the output to shut down. over-temperature protection the ic incorporates an over-tempe rature protection circuit that shuts the ic down when a di e temperature of +160c is reached. normal operation resumes when the die temperature drops below +145c through the in itiation of a full soft-start cycle. during otp shutdown, the ic consumes only 100a of current. when the controller is disabled, thermal protection is inactive; this helps achieve a ve ry low shutdown current of 5a. feedback loop compensation to reduce the number of external components and to simplify the process of determining compensation components, the controller is designed with an internally compensated error amplifier. to make internal compensation possible, several design measures were taken. first, the ramp signal applied to the pwm comparator is proportional to the input voltage provided at the vin pin. this keeps the modulator gain constant with varying input voltages. next, the load current proportion al signal is derived from the voltage drop across the lowe r mosfet during the pwm time interval and is subtracted from the amplified error signal on the comparator input. this creates an internal current control loop. the resistor r cs connected to the isen pin sets the gain in the current feedback loop. the following expression estimates the required value of the current sense resistor depending on the maximum operating load current and the value of the mosfet r ds(on) as shown in equation 8 . choosing r cs to provide 30a of current to the current sample and hold circuitry is recommended but values down to 2a and up to 100a can be used. due to the current loop feedback, the modulator has a single pole response with -20db slope at a frequency determined by the load by using equation 9 . where r o is load resistance and c o is load capacitance. for this type of modulator, a type 2 compensation circuit is usually sufficient. figure 32 on page 18 shows a type 2 amplif ier and its response, along with the responses of the current mode modulator and the r ocset r ds on ?? ?? i oc ?? 0.7 3.5r cs + ------------------------------------------ - k ? ?? = (eq. 7) r cs i max ?? r ds on ?? ?? 30 ? a ---------------------------------------------- - ? (eq. 8) f po 1 2 ? r o c o ?? -------------------------------- - = (eq. 9)
isl8117 fn8666 rev 4.00 page 18 of 24 apr 19, 2018 converter. the type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. high amplifier zero frequency gain and modulator gain are chosen to satisfy most typica l applications. the crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. the only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. with this type of compensation, plenty of phase margin is easily achieved due to zero-pole pair phase ?boost?. conditional stability may occur only when the main load pole is positioned to the extreme left side on the frequency axis due to excessive output filter capacitance. in this case, the esr zero placed within the 1.2khz to 30k hz range gives some additional phase ?boost?. some phase boos t can also be achieved by connecting capacitor c 3 in parallel with the upper resistor r 1 of the divider that sets the outp ut voltage value. refer to ? output voltage programming ? on page 14 . layout guidelines careful attention to layout requirements is necessary for successful implementation of an isl8117 based dc/dc converter. the isl8117 switches at a very high frequency and therefore the switching times are very short. at these switching frequencies, even the shortest trace has significant impedance. also, the peak gate drive curre nt rises significantly in an extremely short time. transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, generate emi, and increase device overvoltage stress and ringing. careful component selection and proper pc board layout minimizes the magnitude of these voltage spikes. there are three sets of critical components in a dc/dc converter using the isl8117: 1. controller 2. switching power components 3. small signal components the switching power components are the most critical from a layout point of view because they switch a large amount of energy, which tends to generate a large amount of noise. the critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. a multilayer printed circuit board is recommended. layout considerations 1. the input capacitors, upper fet, lower fet, inductor, and output capacitor should be plac ed first. isolate these power components on dedicated areas of the board with their ground terminals adjacent to one another. place the input high frequency decoupling ceramic capacitors very close to the mosfets. 2. if signal components and the ic are placed in a separate area to the power train, it is recommended to use full ground planes in the internal layers with shared sgnd and pgnd to simplify the layout design. ot herwise, use separate ground planes for the power ground an d small signal ground. connect the sgnd and pgnd together close to the ic. do not connect them together anywhere else. 3. the loop formed by the input capacitor, the top fet, and the bottom fet must be kept as small as possible. 4. ensure the current paths from the input capacitor to the mosfet, to the output inductor and the output capacitor are as short as possible with ma ximum allowable trace widths. 5. place the pwm controller ic close to the lower fet. the lgate connection should be short and wide. the ic can be best placed over a quiet ground area. avoid switching ground loop currents in this area. 6. place vcc5v bypass capacitor very close to the vcc5v pin of the ic and connect its ground to the pgnd plane. 7. place the gate drive componen ts - optional boot diode and boot capacitors - together near the controller ic. 8. the output capacitors should be placed as close to the load as possible. use short wide copper regions to connect output capacitors to load to avoid inductance and resistance. 9. use copper filled polygons or wide short traces to connect the junction of upper fet, lower fet, and output inductor. also keep the phase node connectio n to the ic short. do not unnecessarily oversize the copper islands for the phase node. because the phase nodes are subjected to very high dv/dt voltages, the stray capa citor formed between these islands and the surrounding circuitry will tend to couple switching noise. 10. route all high speed switching nodes away from the control circuitry. figure 32. feedback loop compensation f z 1 2 ? r 2 c 1 ?? ------------------------------ - 10khz == (eq. 10) f p 1 2 ? r 2 c 2 ?? ------------------------------ - 600khz == (eq. 11) r 1 r 2 c 1 c 2 f po f zf p f c modulator ea converter type 2 ea g ea = 18db g m = 23.5 db
isl8117 fn8666 rev 4.00 page 19 of 24 apr 19, 2018 11. create a separate small anal og ground plane near the ic. connect the sgnd pin to this pl ane. all small signal grounding paths including feedback resi stors, current limit setting resistor, soft-starting capacitor, and en pull-down resistor should be connected to this sgnd plane. 12. separate the current sensing trace from the phase node connection. 13. ensure the feedback connection to the output capacitor is short and direct. general powerpad design considerations the following is an example of how to use vias to remove heat from the ic. it is recommended to fill the thermal pad area with vias. a typical via array fills the thermal pad footprint such that their centers are 3x the radius apart from each other. keep the vias small but not so small that their inside diam eter prevents solder wicking through during reflow. connect all vias to the ground plan e. it is important the vias have a low thermal resistance for ef ficient heat transfer. it is important to have a complete connection of the plated through-hole to each plane. component selection guideline mosfet considerations the logic level mosfets are chosen for optimum efficiency given the potentially wide input voltage range and output power requirement. two n-channel mosfets are used in the synchronous-rectified buck converters. these mosfets should be selected based upon r ds(on) , gate supply requirements, and thermal management considerations. power dissipation includes two lo ss components: conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty cycle (see equations 12 and 13 ). the conduction losses are the main component of power dissipation for the lower mosfet. only the upper mosfet has significant swit ching losses, because the lower device turns on and off into near zero voltage. the equations assume linear voltage current tran sitions and do not model power loss due to the reverse recovery of the lower mosfet?s body diode. a large gate-charge increases the switching time, t sw , which increases the upper mosfets? swit ching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications. output inductor selection the pwm converter requires an output inductor. the output inductor is selected to meet the output voltage ripple requirements. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current and the output capacitor(s) esr. the ripple voltage expression is given in the capa citor selection section and the ripple current is approximated by equation 14 : the ripple current ratio is usually from 30% to 70% of the full output load. output capacitor selection the output capacitors for each output have unique requirements. in general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. selection of output capacitors is also dependent on the output inductor, so some in ductor analysis is required to select the output capacitors. one of the parameters limiting the converter?s response to a load transient is the time required for the inductor current to slew to its new level. the isl8117 will provide either 0% or maximum duty cycle in response to a load transient. the response time is the time interval required to slew the inductor current from an initial current value to the load current level. during this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). minimizing the response time can minimize the output capacitance required. al so, if the load transient rise time is slower than the inductor response time, as in a hard drive or cd drive, it reduces the requirement on the output capacitor. the minimum capacitor value required to provide the full, rising step, transient load current duri ng the response time of the inductor is shown in equation 15 : where c out is the output capacitor(s) required, l o is the output inductor, i tran is the transient load current step, v in is the input voltage, v o is output voltage, and dv out is the drop in output voltage allowed during the load transient. high frequency capacitors initially supply the transient current and slow the load rate of change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the equivalent series resistance (esr) and voltage rating requirements as well as actual capacitance requirements. figure 33. pcb via pattern p upper i o 2 ?? r ds on ?? ?? v out ?? v in --------------------------------------------------------------- i o ?? v in ?? t sw ?? f sw ?? 2 --------------------------------------------------------- - + = (eq. 12) p lower i o 2 ?? r ds on ?? ?? v in v out C ?? v in --------------------------------------------------------------- --------------- - = (eq. 13) ? i l v in v out C ?? v out ?? f sw ?? l ?? v in ?? --------------------------------------------------------- - = (eq. 14) c out l o ?? i tran ?? 2 2v in v o C ?? dv out ?? ---------------------------------------------------------- - = (eq. 15)
isl8117 fn8666 rev 4.00 page 20 of 24 apr 19, 2018 the output voltage ripple is due to the inductor ripple current and the esr of the output capacitors as defined by equation 16 : where ? i l is calculated in equation 14 . high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load circuitry for specific decoupling requirements. use only specialized low-esr capacitors intended for switching regulator applications for the bu lk capacitors. in most cases, multiple small case electrolytic capacitors perform better than a single large case capacitor. the stability requirement on the se lection of the output capacitor is that the ?esr zero? (f z ) is between 2khz and 60khz. this range is set by an internal, single compensation zero at 8.8khz. the esr zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the control loop. this requirement is shown in equation 17 : in conclusion, the output capaci tors must meet the following criteria: 1. they must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient. 2. the esr must be sufficiently low to meet the desired output voltage ripple due to the output inductor current. 3. the esr zero should be placed in a rather large range, to provide additional phase margin. the recommended output capacitor value for the isl8117 is between 100f to 680f, to meet the stability criteria with external compensation. use of al uminum electrolytic (poscap) or tantalum type capacitors is recommended. use of low esr ceramic capacitors is possible with loop analysis to ensure stability. input capacitor selection the important parameters for the input capacitor(s) are the voltage rating and the rms current rating. for reliable operation, select input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. the ac rms input current varies with the load given in equation 18 : where dc is duty cycle of the pwm. the maximum rms current supplied by the input capacitance occurs at v in = 2 x v out , dc = 50% as shown in equation 19 : use a mix of input bypass capacitors to control the voltage ripple across the mosfets. use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors can be placed very close to the mosfets to suppress the voltage induced in the parasitic circuit impedances. solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge current at power-up. v ripple ? i l esr ?? = (eq. 16) c out 1 2 ? esr ?? f z ?? ----------------------------------- - = (eq. 17) i rms dc dc 2 C i o ? = (eq. 18) i rms 1 2 -- - i o ? = (eq. 19)
isl8117 fn8666 rev 4.00 page 21 of 24 apr 19, 2018 revision history the revision history provided is for informational purp oses only and is believed to be accurate, but not warranted. please go to web to make sure you have the latest revision. date revision change apr 19, 2018 fn8666.4 updated related literature on page 1. ordering information table on page 3: added tape and reel parts and tape and reel column. updated note 1. added isl8117demo3z and isl8117demo4z. page 19: output capacitor selection section, fourth paragraph, first sentence: changed ?the maximum capacitor value. . .? to: ?the minimum capacitor value. . .? removed about intersil section. updated disclaimer. updated pod l16.4x4a from rev 3 to rev 4, changes since rev 3: updated bottom view: 2.40 to 2.45 +0.10/-0.152.45 (2 dimensions) updated typical recommend land pattern: 2.40 to 2.45 jun 4, 2015 fn8666.3 description, page 1 - changed "with 13 ex ternal components" to "with 10 external components". on page 3, en pin description - changed "when the voltage on the pin reaches 1.3v, the output becomes active" to "when the voltage on the pin reaches 1.6v, the output becomes active". on page 14, right column, changed "thermal protection may be triggered if die temperature increases above +150c due to excessive power dissipation" to "the rmal protection may be triggered if die temperature increases above +160c due to excessive power dissipation". on page 14, right column, changed "when the en pin voltage is hi gher than 1.3v, the controller is enabled to initialize its internal circuit" to "when the en pin voltage is higher than 1. 6v, the controller is enabled to initialize its internal circuit ". may 12, 2015 fn8666.2 replaced figures 1, 4, and 5. updated the mod/sync pin description on page 3. may 6, 2015 fn8666.1 added htssop package/part information throughout datasheet. on page 7, updated ?ivinop? parameter typical value from ?3ma? to ?2.5ma?. added 2nd paragraph to ?overvoltage protection? section on page 17. apr 10, 2015 fn8666.0 initial release
isl8117 fn8666 rev 4.00 page 22 of 24 apr 19, 2018 package outline drawing l16.4x4a 16 lead quad flat no-lead plastic package rev 4, 7/17 for the most recent package outline drawing, see l16.4x4a .
isl8117 fn8666 rev 4.00 page 23 of 24 apr 19, 2018 package outline drawing m16.173a 16 lead heatsink thin shrink small outline package (htssop) rev 1, 2/15 0.09 to 0.20 see detail "x" detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burr s. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include inter lead flash or protrusion. inter lead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include damba r protrusion. allowable protrus ion shall be 0.08mm total in excess of dimension at maximum materia l condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0.25 1.00 ref (1.45) 16 2 1 3 8 b 1 3 9 a pin #1 i.d. mark 5.00 0.10 6.40 4.40 0.10 0.65 1.20 max 0.25 +0.05/-0.06 5 c h 0.20 c b a 0.10 c - 0.05 0.10 c b a m 3.00 0.10 3.00 0.10 exposed thermal pad bottom view seating plane 0-8 ( 3.00) for the most recent package outline drawing, see m16.173a .
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"standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale com munication equipment; key financial terminal systems; safety control equipment; etc. unless expressly designated as a high reliability product or a product for harsh environments in a renesas electronics data sh eet or other renesas electronics document, renesas electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artific ial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant s ystems; military equipment; etc.). renesas electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any renesas electronics produc t that is inconsistent with any renesas electronics data sheet, user?s manual or other renesas electronics document. 6. when using renesas electronics products, refer to the latest product information (data sheets, user?s manuals, application n otes, ?general notes for handling and using semiconductor devices? in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by renesas electronics with respe ct to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. renesas electronics disclaims any and all liability for any malfunctions, failure or accide nt arising out of the use of renesas electronics products outside of such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of renesas electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. unless designated as a high reliability product or a product for ha rsh environments in a renesas electronics data sheet or other renesas electronics document, renesas electronics products are not subject to radiation resistance design. you are responsible for impl ementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of renesas electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. you are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, includi ng without limitation, the eu rohs directive, and using renesas electronics products in compliance with all these applicable laws and regulations. renesas electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technologies shall not be used for or incorporated into any products or systems whose manuf acture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you shall comply with any applicable export control laws and regulations promulgated and administered by the go vernments of any countries asserting jurisdiction over the parties or transactions. 10. it is the responsibility of the buyer or distributor of renesas electronics products, or any other party who distributes, d isposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 11. this document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written cons ent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products. 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